Chapter 11


Circuit design, as a creative activity is intrinsically error prone. Designing is making choices. Choices are based on assumptions and simplifications. This is why validating choices is mandatory and has to take place as soon as possible.

Validation is a generic word that applies for any design step where choices are made:

  • Architecture validations
  • Sizing validations

It also applies for the design tools themselves:

  • Design kit validation

And, of course, it applies to the product itself:

  • Silicon validation

Hierarchically speaking:

  • Silicon validation is the top level loop validation.
  • Architecture and sizing validations take place at every level design loop.
  • Design kit validation is outside any loop.

Chronologically speaking:

  • Design kit validation takes place first..
  • Architecture and sizing validations take place all along design.
  • Silicon validation takes place at the end of the first pass in the development loop.

Design kit validation and Architecture validation are addressed in the respective sections. In this chapter, we will introduce the loops validation phases at properly speaking:

  • Sizing validation.
  • Layout validation.
  • Silicon validation.

If validation fails, a debug or troubleshooting phase is required to fix the issues. These phases will be detailed in the next four chapters.

11.1 Sizing validation

In fact, when a design is sized, everything is ready for simulating it. So, sizing validation also validates architecture and is in fact some sort of a complete design verification. Sizing validation is a three steps process:

  • Verification: Running typical simulations in order to check functionality and performance.
  • Characterization: Running a full set of simulations trough voltage, temperature, process and mismatch.
  • Debug: Identifying and fixing issues if any.

11.1.1 Verification

Validating cell functionality means checking that the cell can be set to operate in all the functional modes and that functionality and performances are correct in all the modes. This is normally done at room temperature, nominal supply and typical process.

Prior to design verification, the checklist below can be used to run simple simulation that can lead to eventually modify the cell. This can save iterations in the design loop.

Verification is done with the help of a simulator. If verification fails, the origin of failure has to be found and corrected, and then verification has do be done again.

11.1.2 Characterization

The specification contains a list of items that define cell performances. Characterizing is checking all the specified characteristics, in all the possible environment conditions and in any process case and checking the impact of mismatch through Monte-Carlo simulation. Most of these performances can be checked by simulation, with some limitations and exceptions.

  • Limitations mainly result from non modeled phenomenons and limited model accuracy.
  • Exceptions are mainly caused by accuracy concerns, by non applicable or non existing analysis types.

For each specification item, a test cell should be created. The test cell is a schematic that instances the cell to test, together with stimuli and external components. The goal is to put the cell in the conditions the specification defines for the item to be measured. The cell can then be simulated and the performance can be measured and compared to the specified limits. Checking the entire specification usually requires a set of test cells with different setups, different stimuli or different external components. For each test cell, several types of analysis can be carried out depending on specification item to check. In addition, simulation allows environment conditions such as temperature and supply voltage, but also process case to be changed. Monte-Carlo simulations are also required to check the influence of mismatches.


The result of a characterization can be positive or negative:

  • If the cell complies with its specification, the design can continue with another cell. This situation shows that the design process has converged. It means that the method has been used successfully.
  • If the specification is not met, iterations are required on sizing or on architecture. If this occurs at the first iteration, and especially if only a slight change in sizing can cure the issue, the situation is less that ideal but not too critical.

An unmet specification after a large number of iterations indicates that something went wrong in the design process.

11.1.3 Design Debug

If a specification is not met, a debug process must be started to find the root cause and find a solution. This process is detailed in dedicated chapter: Sizing Validation.

11.2 Layout validation

In modern tools, Layout is usually a safe design phase as tools permanently check the consistency between the sized schematics and the layout. This is a kind of validation. However, a global validation is required to manage a number of possible issues:

  • Hierarchy issues.
  • Parasitic components.

11.2.1 Hierarchy issues

11.2.2 Parasitic components

11.2.3 Layout debug

If something is wrong with the layout, just as for design, a debug session is required. It is detailed in a dedicated chapter: Layout Validation.

11.3 Silicon validation

Validation is not only a binary test to know whether the design complies with its specification or not. If it does not comply, the reason should be identified so as to be fixed. This phase can be called troubleshooting or debugging. Validating the silicon samples is a critical phase. Accuracy and exhaustiveness of this work conditions the future life of the product. Validating a piece of silicon is also a difficult task more several reasons:

  • One goal is to find what’s wrong and the designer hopes and wants to show that his design is good.
  • Another goal is to check that everything works as expected, not only that globally the circuit works.
  • Another goal is to evaluate margins but the samples are what they are and it is not possible to vary the process parameters or the matching data on samples.
  • When validation starts, not only silicon status is unknown but also the test board status is unknown and the control software if any is also in an unknown status.

In order for the silicon validation to be carried out efficiently, a silicon validation phase is required. It is detailed in a dedicated chapter: Silicon Validation.