Welcome / Abstract
1 Part 1 Analog IC Development Introduction
2 Development
3 Design
4 Top-Down design flow
5 Feasibility study
6 Design management
7 Specification
8 Architecture
9 Sizing
10 Implementation
11 Validation
12 Sizing validation
13 Layout validation
14 Silicon validation
15 Troubleshooting
16 Part 2 IC Design Introduction
17 Basic elements
18 Bipolar transistors
19 MOS transistors
20 Common characteristics
21 Resistors
22 Capacitors
23 Inductors
24 ESD Devices
25 Parasitic Components
26 Substrate
27 Package
28 PCB
29 Test
30 Reliability
31 Building blocks
32 Classification
33 Part 3 Design examples
34 MOS follower
35 Constant gm cell
36 Bandgap
37 Voltage regulator
38 Sigma Delta modulator
39 Part 4 Techniques
40 Dependency graph
41 Simulation techniques
42 Robust design
43 Safe design
44 Optimization
45 Part 5 Basic concepts
46 Math for electronics
47 Physics for electronics
48 Electronics for design
50 Material properties
51 Tools

Chapter 13

Layout validation

Layout validation can be thought as a simple task as powerful tools are available to check the layout versus the schematic and to simulate the layout including parasitic components. But this idea is not completely true:

Some parasitic components such as substrate coupling are not managed.
Identifying an issue does not give the solution.

13.1 Floor plan validation

The first step of layout validation, even before layout starts is validating the floor plan.

Floor plan is defined by:

Chip pinout
Top blocks sizes
Parasitic coupling

13.2 Leaf cell validation

This is the well known DRC - LVS - LPE verification trilogy

13.3 Top cell validation

Once every leaf cell is validated, the validation can continue upwards to the TOP cell

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