Chapter 13

Layout validation

Layout validation can be thought as a simple task as powerful tools are available to check the layout versus the schematic and to simulate the layout including parasitic components. But this idea is not completely true:

  • Some parasitic components such as substrate coupling are not managed.
  • Identifying an issue does not give the solution.

13.1 Floor plan validation

The first step of layout validation, even before layout starts is validating the floor plan.

Floor plan is defined by:

  • Chip pinout
  • Top blocks sizes
  • Parasitic coupling

13.2 Leaf cell validation

This is the well known DRC - LVS - LPE verification trilogy

13.3 Top cell validation

Once every leaf cell is validated, the validation can continue upwards to the TOP cell