As already stated, silicon validation is a difficult task.
Roughly, silicon validation is a three steps process:
In the lab, only external signals can be measured easily. Internal signal might be addressed by probing but this requires that special small pads have been intentionally added. Dedicated test hardware is highly recommended to make verification easier, even though it costs some silicon area. The verification time and often the production test time it saves is worth the money. One point to keep in mind is that measuring internal signals can affect circuit operation by adding a significant amount of parasitic capacitance on the signal line.
Basically the plan lists all the measurements to be performed with associated conditions. The goal is ideally to check every spec item from every circuit cell.
A Lab setup consists in hardware and software that are intended to interface the piece of silicon with the external world. The hardware is mainly a board with a socket and a set of power supplies and measurement instruments. The software achieves the interface with the silicon control section if any and can be used to drive measurement instruments in order to automate the characterization. Both the board and the software have to be validated before they can be linked to any piece of silicon.
Validating the board includes items like:
Silicon differs from simulated schematic:
Silicon verification can start only when the lab setup has been verified.
A good practice is to write a day to day validation report summarizing the measurements carried out, the conditions, the equipment, the results, the issues.
Troubleshooting must take place.
After the silicon is validated i.e. all functions and performance are checked in nominal conditions, a characterization phase can take place so as to check statistically and through operating conditions. A good start point is to characterize extensively 10 parts though the full supply voltage range and temperature range. Ideally, parts from different process corners should be characterized.