Bipolar transistors were the first transistors to be created in 1948 by Bardeen, Brattain and Schockley at Bell Labs.
Bipolar transistors behavior is reasonably well described by the so called “Gummel and Poon model”. This model is suitable for calculation and for computation. The designer can use it, at least in a simplified version, for sizing a circuit and simulators use it extensively.
Pins are identified by a letter, E for emitter, B for base and C for collector. Currents in the three pins are identified by the pin letter as IE, IB and IC. Voltages are identified by the two pins letters as VBE, VBC, VCE.
With the figured convention on voltages and currents:
In the symbols shown here, emitter is bottom connection for the NPN and top connection for the PNP. This is the standard convention for drawing schematics with the positive supply at the top and the negative supply at the bottom.
In integrated circuits, transistors have to be isolated from each other. Starting from this constraint, several transistor structures can be implemented. They will be detailed hereafter. Basically, transistors are named:
In all the figures below, only the final and simplified transistor structure is shown, no details are given on process.
In the classic bipolar process, the most standard transistor is the vertical NPN on a P type substrate.
The actual transistors structure is more complex, mainly in order to reduce the parasitic series resistance on collector and base by adding higher doping regions between the access on top and the active region inside the transistor.
In the classic bipolar process, PNPs cannot be implemented as both vertical and isolated on P substrate. Isolated PNPs are lateral.
For efficiency reasons, actual transistors differ a bit from this simplified drawing. Usually, collector P area is given a ring shape surrounding the emitter. In order to prevent the parasitic PMOS to turn on, a good practice is to have the emitter metal connection overlapping the N base region between emitter and collector. In order to achieve the best possible current gain, the emitter should be highly doped. If some other P layers are available and compatible in size and depth, the can be added to the emitter region to improve the lateral PNP current gain.
In the classic bipolar process, vertical PNPs cannot be isolated on a P substrate, they share the collector in common.
Implementing a vertical PNP could be thought just as the dual of the vertical NPN implementation. It is not usually the case as most of the time, NPNs are required as well. So implementing a vertical PNP on a P substrate requires one more isolating N well. In addition, the three active layers are obviously not the same as for the NPN. As a result, such a process is more complex and more expensive than the simpler classic process.
Just as for vertical NPNs, actual transistors are more complex with added regions mainly intended to reduce parasitic series resistance.
Without special process options, only lateral and substrate PNPs are available in CMOS processes. With appropriate options, CMOS processes can become true BiCMOS processes with good performance bipolar transistors.
The vertical bipolar transistor base is very thin. The emitter to collector distance is very small, smaller the the drain to source distance in a MOS from the same generation. Base thickness has been below 0.1 μ m
for more than 20 years. This has been possible because base thickness is not defined by lithography but by the difference between two junction depths. And this is also allowed even with a significant breakdown voltage since only the base collector is reverse biased and the depleted region can extend in the collector allowing high voltages even if the base is this.
Another consideration is related to current density. As the current flows vertically, it uses all the emitter area which can be made significant. In a MOS transistor, the current flows horizontally in a very thin inverted layer. Achieving a significant area for the current to flow implies a very large transistor.
Equations are written for NPNs. For PNPs, voltages and currents are multiplied by -1. Equations apply for the transistor whatever its structure
First, let's define:
k=1.38 ⋅ 10^-23 is Boltzmann's constant in J / K,
q=1.6 . 10^-19 is the electron's charge in C
and T is the absolute temperature in K.
VT is known as the “thermodynamic voltage”. At room temperature, VT ≃ 26mV
The collector current that actually flows from collector to emitter depends on VBE and VBC the following way:
For the base current that actually flows from base to emitter, expression is:
As a result, emitter current is the sum of collector current and base current. In order to satisfy the Kirchhoff Current Law, emitter current is negative.
It is fundamental to see that, in usual operating conditions, collector current and base current result from base-emitter voltage. As a result, the current gain, usually noted β is an indirect effect.
These equations show five model parameters:
For vertical transistors, the NF and NR parameters are close to 1. For lateral transistors, NF and NR are larger and cause a non ideal behavior that make these transistors unsuitable to design band-gaps.Example:
With this basic model, and with the following parameter values:
We can plot the following curves:
The basic static model describes a somewhat ideal transistor but already includes the saturation effect. Both the collector current and the current gain fall to zero when VCE tends to zero. But the output impedance is infinite and current gain does not depend on current value.
Now we will step by step introduce the effects that will make our transistor more realistic:
This effect describes the output resistance. The collector current is primarily defined by the base-emitter voltage but also depends on the collector-base voltage. The equation is shaped to show an Early factor and the basic collector current.
This equation adds two model parameters:
Early effect leaves base current unaffected. So, collector current and current gain will depend on VCE.
Lets add the following parameter values to our model:
The previous curves change a bit:
Now, our transistor shows a finite output resistance, a current gain that depends on VCE but still no significant change of current gain with collector current except that caused by the small VBE change over the current range.
VAF appears like the negative voltage at which the linear extrapolation of IC vs. VCE would tend to zero. So, the higher VAF, the higher the output resistance.
This effect describes the current gain reduction at high currents. The equation is shaped to show an injection factor and the basic collector current.
Again, the equation has been shaped to display a coefficient applied to the basic current.
This equation adds two model parameters:
It can be noted that High Injection effect does not make any change on base current.
Now let's remove VAF and VAR from our model and add the following parameter value:
The previous curves change again:
Now, our transistor exhibits a current gain that depends on the collector current.
IKF appears like the collector current at which current gain is divided by 2.
Of course, in a real transistor the two effects are combined. So far we have considered them separately for the sake of clarity and to provide a better understanding.
Early and High Injection effects combine simply by multiplying the coefficients.
Inevitably, parasitic resistances exist on the three pins. These resistances result from connections and semiconductor material between access points and internal region where the transistor effect takes place.
The three resistances, as made from semiconductor material are subject to temperature variations.
A junction capacitance results from two terms:
The two terms sum up to give the overall junction capacitance. This sounds like the two terms correspond to two capacitors connected in parallel.
This capacitance exists in both forward and reverse biasing. It is the depleted region capacitance. It depends on the voltage. In an IC, bipolar transistors have three junctions:
All these junctions behave the same, they differ by the parameters of the equations. Lets index equations and variables by index "IJ" standing for "BE", "BC" and "CS".
There are basically two regions with a boundary defined by parameters "FC" and "VJY" :
Let's consider a junction with the following parameters:
(These parameters are similar to those of the popular 2N2222 transistor BE junction but they have been renamed to fit with our notation)
Let's plot CXY versus VXY:
As can be seen, CJY corresponds to capacitance under 0V bias.
In the reverse bias region, capacitance decreases under the control of parameters VJY and MJY. This phenomenon is used in varicap diodes.
In the forward region, one can see the change of behavior caused by parameters FC and VJY: The curve shape looks a bit different.
A rule of thumb is that when forward biased (VBE around 0.7 V), Base-Emitter transition capacitance is about twice the value of parameter CJE.
This capacitance exists only in forward biasing. It results from the minority carriers stored in the junction. It depends on the current. Only forward biased junctions exhibit diffusion capacitance. Normally, only the Base-Emitter junction is forward biased but in saturation, the Base-Collector is forward biased too.
The three junctions in a transistor, BE, BC and CS, if forward biased to a sufficient voltage have some forward current IX flowing through. As a result, because of the carriers crossing the junction in some transit time TX, an amount of charge is present. The associated capacitance is:
This capacitance is proportional to the junction forward current. In fact, TX slightly depends on current but this is a second order effect.
For transistor 2n2222,published TF is about 400 ps. Fundamental question is:
At which collector current does the diffusion capacitance equal the transition capacitance (about twice CJE i.e. 45 pF.
The answer is IC = 2.86 mA.
Now if we plot CTX, CXY and the sum versus current over a couple of decades around that current for which CTY = CXY:
We can see that Diffusion and Transition curves cross around 3 mA, not so far from our estimation.
As announced, at low currents (or in reverse bias), junction capacitance is governed by transition while at high currents it is governed by diffusion.
We will use this characteristics extensively later on when it comes to calculate cutoff frequencies.
When the bipolar transistor is operated in the forward region, expressions simplify:
The model as described so far, even the simplified version are non linear. Nowadays with computers and simulation we can deal with non linear computation but in the past it was much more painful. The small signal model is a linearized model that is only valid for small variations around the operating point. This model is helpful as it allows calculation and helps sizing.
For the bipolar transistor, current flowing from collector to emitter depends on voltage between base and emitter.
Transconductance can be defined as:
For a bipolar transistor, transconductance depends only on collector bias current and on temperature. No process parameter influences the bipolar transconductance. There is just a restriction on the current range for this to be true. Collector current must be larger than leakages and it must be low enough so that degeneration by emitter resistance is negligible. Usually, for a given transistor, this is true over more than six decades of collector current.
Input resistance is defined by vBE and iB as: