As already stated, in an integrated circuit, bulk components are isolated from each other by reverse biased junctions. So, in an integrated circuit, there are many isolation diodes. These diodes are normally reverse or zero biased. As such they exhibit:
Management of isolation diodes depends on Design Kit. Checking isolation diodes models is an important step in validating a Design Kit.
Diodes between components and Wells are usually managed properly.
However, Well diodes are usually not taken into account as they depend on components grouping and are not actually known during Front-End design. These diodes have to be managed, often manually by the designer.
Some design kits include isolation diodes when layout is done by running a parasitic extraction program.
In integrated circuits, parasitic resistors are mostly located inside components and they are usually taken into account by the models. Routing parasitic resistors can be extracted by extraction tools after the layout is done and can be taken into account in simulations at this time. The major effects of routing parasitic resistances are:
I.R. drops result in performance changes.
For instance, if a current mirror is improperly connected to a supply rail, I.R. drops can result in an output current that can be significantly different from the expected value.
Two isolated conductors exhibit some capacitance between each other. When this capacitance is unexpected, it is called parasitic capacitance.
In a circuit, adding some capacitance at some places can modify behavior or at least performance.
Apart from isolation diodes, parasitic capacitance are mainly due to connections. Routing capacitance can be extracted by extraction tools after the layout is done and can be taken into account in simulations.
Just as for parasitic resistance, thinking about parasitic capacitance impact during design and layout avoids doing the job again even though extraction programs can show the issue before running the silicon.
As for parasitic resistances, validating parasitic capacitance extraction requires walking the design flow through layout and extraction on simple structures that validate the extraction.
Several situations have to be checked:Overlapping connections
In this situation, both the area capacitance and the fringe capacitance can be checked.Non-overlapping connections
In this situation only fringe capacitance can be checked.
In this case, only the mix of area and fringe capacitance can be checked.
This test is intended to check if a distinction is made between substrate and well for the cold side of the parasitic capacitance.
This test is intended to check if screening effect is taken into account.
In integrated circuits, parasitic PMOS transistors exist in every place where an N type region is located between two P type regions if a metal line overlaps the N region. The same exists for an NMOS by just swapping N type and P type regions.
Usually, threshold voltages for these parasitic MOS are high and they are not a concern. However, in high voltage applications, parasitic MOS can create undesired currents and can result in trouble.
Unfortunately, parasitic MOS are usually not modeled nor taken into account by extraction. Sometimes, they are flagged by verification programs and it is the designer's responsibility to check whether they can cause issues.
If no data are supplied by the silicon manufacturer, the most secure approach is to implement the various parasitic MOS transistors in a test circuit and to measure their threshold voltages.
In integrated circuits, parasitic bipolar transistors exist at any place where N, P regions are arranged so as to create NPN or PNP structures. As an example, a parasitic substrate PNP is associated to each vertical NPN:
This parasitic PNP draws current from NPN base to the P substrate if the NPN is driven into saturation i.e. if base-collector junction is forward biased. This current increases the NPN base current further decreasing the apparent beta value, but it also modifies the local substrate voltage which can, in turn affect the circuit behavior. More generally, parasitic bipolar transistors, if they are turned on, can create parasitic currents that can modify the circuit behavior or performances.
When a PNP and a NPN are connected in a particular way, they implement a different device: The Thyristor.
The thyristor is a trigger device that can be turned on but that requires disconnecting the supply to turn off. This can be analyzed as follows. If the NPN, for instance is off, its collector current is very small. This current is multiplied by the PNP β
and applied to the NPN base. It is then multiplied by the NPN β
. If the product of betas is lower than 1, the circuit remains in the off state. Usually, the β
curve for a bipolar transistor shows a significant value in a given current range and drops at high and low currents. Normally, when the transistors are off, the currents are low enough so that the betas are lower than 1. If for any reason, some current is injected, the collector currents increase. If the collector currents are large enough for the product of betas to be larger than one, the current increase and increase until it reached the high value for which the product of betas falls below 1. At this point if the current increases further, the betas decrease so the current decreases. If current decreases, the betas increase so the current increases. This is a stable point. The only way to stop the current is either turning the supply off or shorting briefly the base-emitter junction of one transistor.