Chapter 26

Substrate

In integrated circuits, all the components are implemented by various physico-chemical techniques inside a common substrate that achieves a mechanical and electrical function.

• The substrate is thick enough to allow wafer handling throughout the manufacturing process.

• The substrate is made from silicon for most products even though some other possibilities exist such as gallium arsenide for very high frequency applications or silicon carbide for very high temperature and radiation hardened applications. Silicon On Insulator (SOI) can be used for some high performance applications. In all but the SOI circuits, components are isolated from each other by reverse biased diodes. In SOI, isolation is performed by a dielectric layer.

All the components have then a parasitic capacitance to the substrate. This does not really mean a parasitic capacitance to ground as it is the case on a PCB with a ground plane. The reason for that is that substrate resistivity is much higher than copper resistivity. So, all the parasitic capacitances in fact connect to a resistive network that is connected to ground at some places. This resistive network causes coupling between cells that are supposed to be independent.

There is no general approach to the substrate coupling issue. However, in any case, coupling is a three steps process:

• Some cells inject parasitic signals into the substrate network.
• The network carries these signals with attenuation.
• Some cells receive parasitic signals from the substrate network.

Addressing substrate issues is usually dealing with the three steps:

• Reducing injected parasitic signals. “Generator” side.
• Optimizing attenuation by substrate. Transmission layer.
• Reducing sensitivity to substrate signals. “Receiver” side.

Quotes are used since any cell can be both a generators and a receiver.

26.1 Reducing generation

Two kinds of parasitic signals are injected in the substrate.

• DC coupled signals

• AC coupled signals

26.1.1 DC coupled substrate signals

These are substrate current from devices like isolation diodes, parasitic bipolar transistors and MOS transistors. Isolation diodes should be kept reverse biased, bipolar transistors should be kept away from saturation to avoid DC currents to be injected in the substrate. This is not always possible. For MOS transistors, ionization current cannot be avoided in any case but it is usually low.

26.1.2 AC coupled substrate signals

These are substrate currents from reverse biased isolation junctions and other parasitic capacitors. The injected currents amplitude is:

• Proportional to the voltage swing.
• Proportional to the parasitic capacitance.
• Proportional to frequency.

There is not much to do with these parameters but the best must be done. Probably the best solution is to choose a differential structure. When two signals of opposite phase inject in the substrate, the sum is theoretically zero. This is not true practically as the two signals cannot be located exactly at the same place and parasitic capacitors are not perfectly matched. However, injected signal is significantly reduced, often by an order of magnitude.

For routing parasitic capacitance, differential signals inject less current. In addition, a shielding by the first metal layer or by poly can improve the situation.

Any cell in an IC should be characterized in terms of what it injects in the substrate.

26.2 Optimizing attenuation

Basically, substrate attenuation results from a “pi” structure:

This attenuator has one coupling branch and two decoupling legs.

• Each decoupling leg has to be connected to reference potentials of its cell which can be on chip or outside, on the board. Decoupling leg impedance completely depend on the case. Obviously, it has to be minimized.
• Coupling branch resistance is more tricky. The only accurate solution is a true 3D simulation. This tool can be used to find some rules of thumb that will be summarized later.

26.2.1 Coupling resistance

Let's run some experiments using a 3D simulator to estimate coupling resistance values:

26.2.1.1 Influence of injector size

If a current is injected punctually at the surface of a large, homogeneous and isotropic block of material with a given resistivity, constant voltage surfaces are half spheres. The resistance between two sphere halves with radius R1 and R2 ( R2>R1 )

26.2.1.2 Influence of distance

26.3 Reducing sensitivity

There are basically two techniques to reduce the “receiver” sensitivity:

• Use an intrinsically low sensitivity architecture such as a differential circuit. The incoming parasitic signal couples identically to the two paths of the differential circuit and is significantly attenuated.
• Use of shielding for signal routing lines. Long signal lines should be routed in metal 2 while a metal 1 shield should connect to the common mode reference potential.