In this chapter, several techniques using a circuit simulator such as SPICE or its derivatives are described. These techniques address some of the tough issues a designer faces in his/her day to day work.
In CMOS circuits, a common issue is “floating gates”.
If a CMOS inverter input is driven by a weak node, it may bias so that a significant current flows through.
In normal operation this phenomenon usually does not take place, but occurrence in power down or standby modes has proved to be a cause for redesigns.
Normally, true floating gates i.e. gates connected to nothing are detected by design checkers. But gates driven by weak nodes are not.
A weak node exists in situations like tri-state outputs when disabled. The voltage on such a node is undefined. More precisely, the voltage depends on the leakage currents of all the devices connected to the node. These leakage currents are subject to change from part to part, with temperature and through time.
Standard simulation may not show the issue.
A method that would reveal weak nodes would reduce the redesigns they may cause.
The method suggested here uses an internal parameter commonly available in most simulators. This parameter is often called “gmin” after SPICE used this name.
Gmin defines the minimum conductance of any semiconductor device non-isolated branch. This is equivalent to saying that any non-isolated pair of nodes in a semiconductor device has a 1/gmin resistor in parallel.
Graph shows drain-source resistance with VGS=0 for gmin=1e-6;1e-9;1e-12.
Clearly, if some current flows in the device, dynamic resistance is lower than 1/gmin but in no case it can be larger than 1/gmin.
If the same is done with a gate source branch, no such phenomenon occurs, current is zero.
If two instances are connected in parallel, dynamic resistance never exceeds 1/(2.gmin). If a multiplier is used, only one branch exists and dynamic resistance never exceeds 1/gmin. In other words, one gmin conductance is added per device branch whatever the device size is.
But, on the other hand, additional conductance from the device itself depends on device size.
This method provides good confidence in a circuit AC stability even in situations where the source of instability is hidden deep in the circuit, in places like bias cells or in case of multiple interacting loops. This method is both fast, efficient and analytical. Not only does it reveal instabilities but also it identifies the source of instability.