Chapter 42

Robust design

A robust design is a design that survives process tolerances and provides a consistent manufacturing yield over time. Techniques exist that can lead to robust designs.

42.1 General principle

The underlying idea is that it is possible to design a circuit in such a way that its performance is made insensitive to process parameters in a given distribution range. More precisely, the idea is that within a given process parameters distribution range, the circuit performance can stay within specification limits.

If this is possible, then any chip with process parameters within range is good and the yield is as good as possible. Additionally, it is possible to push the design closer to the limits of the process parameter distribution and then to improve the performance.

42.2 Introduction

The functionality and performances of an analog cell mainly depends on bias, component geometry and process parameters.

The normal process tolerance results in process parameters spreading. These parameters are different from lot to lot, from wafer to wafer and from device to device. There is no possible action from the designer to prevent this spreading.

The component geometry can be chosen at design level so as to minimize undesired effects. But when chosen, apart from manufacturing tolerance, the component geometry is the same for all the chips and cannot be used to compensate for parameter variations.

The bias point is a set of electrical variables that is chosen by the designer in order to meet the circuit performance. Of course, the bias point is sensitive to process parameters. If no special care is taken, the bias point spreading is added to the active components spreading and the result is poor. On the other hand, some compensation or feedback mechanism can be added in the bias system so that the result is improved. Generally, it is possible to improve both performance and yield. 

42.3 Implementation.

There are basically four different techniques that can be used to improve the design robustness. Of course, these techniques are frequently mixed together to obtain the best possible result. These four techniques are :

  • Using low sensitivity architectures.
  • Compensating for tolerances.
  • Using feedback.
  • Trimming to compensate process.


42.3.1 Low sensitivity architectures. 

It is a very common situation that the designer can choose from several solutions in a given design situation. At properly speaking, no real choice can take place if only one solution exists. 

Some solutions exhibit intrinsically a low sensitivity to some design variables. Usually, the component count is a little bit higher for these solutions than for less robust solutions.

Selecting these solutions naturally results in robust solutions.

42.3.1.1 Example of low sensitivity solution. 

In a situation where a designer has to use a bipolar current mirror operating at a given current I, several types of mirrors can be used :

  • Simple current mirror.
  • Buffered current mirror.
  • Degenerated current mirror.

42.3.1.2 Simple current mirror

In a simple current mirror, the structural current error is : \Delta I=\frac{2\cdot I}{\beta}

Where \beta
is the bipolar transistor current gain.

The output resistance is : ROUT=\frac{VAF}{I}

where VAF is the bipolar transistor Early voltage.

42.3.1.3 Buffered current mirror

In a buffered current mirror, the structural current error is : \Delta I=\frac{2\cdot I}{\beta^{2}}

where \beta
is the bipolar transistor current gain. the output resistance is not modified.

For a \beta
ranging from 50 to 200, the simple mirror can exhibit 4 % current error while the buffered version will never exceed 0.08 %.

No difference between these two solutions regarding the output resistance.

42.3.1.4 Conclusion

So, the buffered mirror is a better solution, at the expense of an additional transistor. 

42.3.2 Compensation techniques. 

The principle of the compensation techniques is based on the fact that the relative tolerance in an integrated circuit is much tighter than the absolute tolerance. For example, a resistor value is as inaccurate as +/- 20 %, but in a given chip, the ratio of two resistor values is usually better than 1%.

If a cell characteristics depends on ratios rather than absolute values, the design will be more robust. 

42.3.3 Feedback techniques. 

The general theory of feedback shows that the closed loop gain of a loop exhibiting a direct path gain A and feedback gain B is : If A.B is much larger than 1, then . A is usually implemented using transistors and the value of A can suffer large tolerances. B is usually a ratio of resistors and can be reasonably accurate. Even if A is inaccurate, G can be accurate provided the fact A is large enough.

42.3.3.1 Example of feedback technique 

Back to the current mirror example. The output resistance of a degenerated current mirror is : where RE is the emitter resistance and VT the thermal voltage, 26 mV at room temperature. This is an effect of the feedback.

Selecting the product RE.IE properly results in increasing the output resistance, reducing the dependence of the output current to the output voltage.

So the degenerated mirror is a better solution at the expense of two additional resistors and a higher saturation voltage.

42.3.4 Trimming techniques

These techniques are used when absolute values cannot be avoided. An example is a filter time constant. The time constant depends on actual R and C values. For given R and C in a process:

If tolerance on time constant has to be smaller than natural value from process, Trimming, also called calibration is required. 

Trimming requires that any element to be trimmed is build from discrete values and switches. Since process centering is common to the whole chip, switch control can be done by a bus.

There are basically two options for trimming:

  • Final test trimming
  • Real time trimming

42.3.4.1 Final test trimming

This technique is suitable when target parameter is stable with respect to time and temperature.

In this case, parameters can be measured during chip final test and trimming bus value can be computed. This requires that the chip has some non volatile memory to store the bus value. As there are usually not many bits to store, the NVM can be implemented as fuses or zapped zeners if no true NVM is available. Of course, if E2PROM is available, it can do the job.

42.3.4.2 Real time trimming

In case the parameters is not stable versus time or temperature, or in case no non volatile memory is available, real time trimming must be considered. In this case, parameter must be measured in real time or at least often enough, for instance each time the circuit is turned on.

The problem is that an accurate reference is required to measure the target parameter.

As an example, if the circuit uses a crystal for clocking and requires to trim an RC product, an RC oscillator can be built and its frequency can be measured using the crystal as a reference. Then the RC product can be trimmed in real time by an on chip state machine. 

42.4 Unexpected consequences of the robust by design approach.

When the various techniques resulting in a robust design are combined together, the design can be very insensitive to the component parameters.

It can be so insensitive that even if one component in the design is nearly failing, the cell will operate properly. Such a part will not be rejected during the production test but could fail quickly in the application if the nearly failing component actually fails after some hours of operation.

In other words, the techniques used to improve the production yield can hide some failure mechanisms and result in early failures in the application.

This means that special attention has to be paid to test. Not only has the operation to be checked, but also margin must be evaluated. It can be necessary, sometimes to open the loops or to check operation over a range of bias values etc…

If real time trimming is used, all the trimming values have to be checked during final test since it is difficult to define which value will be used during the product life.

All this impacts the test time and the test hardware inside the circuit and then impacts the product cost.

So, finally, if only cost is the concern, a balance must be found between reaching a good yield to reduce cost and keeping silicon and test time costs low.

If quality and reliability are real concerns, then this the robust design approach is a must but it comes at some cost.

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